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TSMC revealing details about next gen A14 node

26 points osnium123 2 days ago 6 comments

Abstract at IEDM website below

ABSTRACT

A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.

nwah1 2 days ago | parent

In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.

anamax 1 day ago | parent

There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ is a three-transistor SRAM.

aurareturn 1 day ago | parent

Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.

osnium123 1 day ago | parent

Is the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.

aurareturn 1 day ago | parent

It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.

But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.

It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.

georgeburdell 1 day ago | parent

A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling