Yet another Hacker News

93 points pixelpoet 2 hours ago 34 comments

spwa4 2 hours ago | parent

One thing I wonder about is that these CPUs are just so much faster than their memory controllers. So why not add more? Why don't they have a memory controller per core, for example?

hedgehog 2 hours ago | parent

I think it mostly is for more controllers to be useful that means more PHYs and more actual pins on the package and more traces on the board and more sockets for the memory and... The space and cost of all of that is substantial (to a point, and then it just physically can't be manufactured).

justincormack 2 hours ago | parent

Cost, and especially now, cost of memory! But you can buy AMD chips with 2 controllers (consumer), 4 (threadripper), 6 (8005), 12 (EPYC) memory channels, so in effect you can. Next generation Zen 6 Epyc has 16 channels. Roughly you get about 1 channel per chiplet, but you csn adjust if you need more memory bandwidth by buying fewer chiplets, eg there is an 8 core EPYC if you want to optimisise for bandwidth. But many applications are not bandwidth bound so this isn't the right choice, eg they are IO bound, rarely compute bound.

theandrewbailey 2 hours ago | parent

More memory controllers would add more bandwidth. That can help, but few workloads are bottlenecked by memory bandwidth. (Dual memory channels have been a thing in desktops and laptops since the early 2000s single-core era at least, but newer generations of DDR have increased bandwidth to keep up with increased core counts.) What's really needed is less memory latency (less latency = faster), which has not improved as much as bandwidth.

yread 1 hour ago | parent

Strata is!

O3marchnative 1 hour ago | parent

It's not always trivial to saturate available memory bandwidth. You may need to use more than one core, or you need to carefully consider the topology of the chip you're working with (see lstopo). For example, what if the L3 cache is actually split in two [0]? In such cases, adding more bandwidth doesn't do much for you.

[0] https://en.algorithmica.org/hpc/cpu-cache/sharing/#saturatin...

adgjlsfhk1 1 hour ago | parent

That doesn't help memory latency and most of the time a cpu is waiting it's because of latency, not bandwidth.

Sharlin 1 hour ago | parent

Nine women cannot make a baby in one month.

matja 58 minutes ago | parent

128 cores x 288 pins per DIMM = 36864 pins on your socket, and all the motherboard traces. Good luck with that...

jauntywundrkind 2 hours ago | parent

I was going to be sad than Zen 6c was divergent, but they increased a bunch of OoO structures on Zen 6c? To absorb more potential latency, since the memory is going to be heavier loaded? Ok, that I can appreciate!

It's absolutely wild that adjusting some l3 and using a smaller node goes from 12 to 32 cores for basically the same chip.

I wonder if the CCD will remain as monolithic as it does, for how long? The l3 latency being signficantly higher for 6c (10.3ns zen5 -> 10.7ns z6 -> 16.4ns z6c) feels like a symptom of a broader scaling challenge as the CCD hosts more and more. I can imagine dividing zen 7 or zen8 CCD into partitions, perhaps?

upboundspiral 1 hour ago | parent

Rumor mill says they are going to use costlier interconnect to drive down CCD -> CCD latency in Zen 7+.

joebonrichie 1 hour ago | parent

The instruction level parallelism in the 2-ahead branch prediction is super cool stuff, I know zen5 had this feature but it's kind of crazy that memory is so slow relative to the cores that this complexity is beneficial and worthwhile.

dmitrygr 1 hour ago | parent

It is hilarious that the SPEC2026 graph does not include apple's P-cores. And no, not because they are ARM and not x86, since Graviton is included. It is because their integer & FP scores of 9.8 & 13 respectively absolutely wipe out everything else on this chart.

Remnant44 1 hour ago | parent

I mean, this is a review of the server grade parts. Apple is not exactly selling m chips to hyperscalers right?

Different story when you're talking about the context of a desktop or mobile.

jeffbee 1 hour ago | parent

The same graph has a bar for the Ryzen 9 9950X, though.

trynumber9 1 hour ago | parent

1. Different market

2. What flags & compiler?

3. Can't run Linux on that M5/M6 can we?

dmitrygr 52 minutes ago | parent

1. so is Ryzen 9 9950X

trynumber9 50 minutes ago | parent

1. 9950X isn't on the chart.

The 9950X3D2 was already tested. And was included as comparison point with the fastest possible version of its predecessor (Zen 5).

Some evidence that contextless numbers are meaningless is that your source, David Huang, does include the 9950X but in his results it scores much higher than everything on C&C's chart too (7.25/11.4)

crote 3 minutes ago | parent

Regular Ryzen parts are still reasonably relevant for server use! They support ECC, so there's nothing immediately disqualifying them - see the rebranded "EPYC" 4005 series, for example.

A company like Hetzner isn't going to care an awful lot whether they deploy one big SP5 server or four small AM5 ones for the VM instances they rent out: the only thing that matters is TCO per performance.

Want to stick four NVMe SSDs, a 25Gbit NIC, 256GB of ECC RAM, and some OOB module on a Ryzen board? No problem whatsoever. Want to do the same with an Apple CPU? Ehhh, that's going to be slightly more challenging...

wmf 44 minutes ago | parent

Linux is now (barely) working on M5/M6.

Sopel 54 minutes ago | parent

if you're interested in a fair comparison here's one https://openbenchmarking.org/test/pts/stockfish

dmitrygr 52 minutes ago | parent

Interesting, but seems to lack single-core benchmarks.

Sopel 38 minutes ago | parent

it's not year 2006 anymore

wredcoll 12 minutes ago | parent

So this benchmark lists the following:

> AMD Ryzen 9 9950X 16-Core 63rd 4 40132379 +/- 2530724

> Apple M5 Pro 52nd 5 22108587 +/- 260160

I have absolutely no idea what this is benchmarking or how, but is there any reason not to just read this as the "consumer/low core ryzen" is twice as fast as the m5 pro?

Sopel 10 minutes ago | parent

> I have absolutely no idea what this is benchmarking or how

It's the best chess engine used by millions of people and part of SPEC2026, natively compiled

Remnant44 1 hour ago | parent

What looks like a lot of small balanced improvements to the core itself. Four vector loads per cycle at 256b of less, I wonder if the gather performance is finally acceptable? Another balance example, they actually reduced the number of integer multipliers down to two. I wonder if that was to make diespace for the vnni pipes?

The real star looks like the c cores though. 32 C cores per chiplet with increased l3 cache is impressive

Aardwolf 1 hour ago | parent

> AMD has reduced the number of integer multiply units from three to two, with PDEP and PEXT throughput also falling from three instructions per cycle to two.

Are PDEP and PEXT using the same (parts of) circuits as multiply (they are very different operations...), or are this just two independent drops of circuitry and the wording is just a bit unclear?

adrian_b 13 minutes ago | parent

They are unlikely to share circuits with the multipliers, but the 2 of the 6 execution units that include multipliers must be identical, to simplify layout, and the PDEP/PEXT circuits are allocated to these 2 units, like the multipliers.

bee_rider 1 hour ago | parent

32 cores is a lot of cores in a CCD. Is there a there any smaller logical unit between a CCD and a core, or are you expected to wrangle 32 cores in your lowest NUMA level?

wmf 52 minutes ago | parent

From what I've seen there is no intermediate unit. IMO this is good because it allows larger VMs that don't have to straddle L3s.

deaton 7 minutes ago | parent

32 cores is only on the Zen 6c CCDs. There are 12 cores on the Zen 6 CCDs.

lp92 47 minutes ago | parent

Seems like they are starting to optimize the C core architecture already. Wonder how long it'll be before it becomes its own line up and branding.

ls65536 29 minutes ago | parent

This is amusing since Intel seems to be sort of going in the other direction lately: their efficiency cores are becoming more like their performance cores with each new generation (at least in so far as they are getting wider and more capable of higher clock speeds), and there even seem to be some rumors that the two design trains may get "merged" in the future.